The present invention relates generally to circuitry and protocols associated with operating a memory device, and more particularly, to apparatus for controlling paging operations in a memory device.
FIG. 1 is a simplified functional diagram of a memory device 200 that represents any of a wide variety of currently available memory devices. The central memory storage unit of the memory device 200 is a memory array 202 which is typically arranged in a plurality of banks, with two such banks 204A and 204B shown in the Figure. The memory array 202 includes a plurality of individual memory elements (not shown) for storing data, with the memory elements typically arranged in separately addressable rows and columns. Those skilled in the art oftentimes refer to a collectively addressable subset of the array 202 as a xe2x80x9cpage.xe2x80x9d Typically, a single row of memory elements in a bank of the array constitutes a particular page. In FIG. 1, a plurality of pages 206A and 206B are depicted, corresponding with banks 204A and 204B, respectively.
As known to those skilled in the art, particular locations within the memory array 202 are addressable by Address signals that external circuitry (not shown) provides to the memory device 200. Also, external circuitry provides a plurality of Control or command signals that are used to designate the particular memory access type and/or sequence of memory accesses. As depicted in FIG. 1, a control/address logic circuit 208 receives the Control signals and Address signals, which may be provided in parallel signal paths, serially, or some combination. The control/address logic circuit 208 then applies a plurality of internal control signals to control the timing and sequence of operations accessing the banks 204A and 204B via access circuits 210A and 210B, respectively. Those skilled in the art will understand that the depicted access circuits 210A and 210B represent a collection of various functional circuit components commonly found in memory devices. Examples include row and column address latch, buffer, and decoder circuits, sense amplifiers and I/O gating circuitry, and other well-known circuits adapted for particular memory device implementations. Data written to and read from the memory array 202 is transferred from and to external circuitry via a data I/O circuit 212 and the access circuits 210A and 210B.
When access to a particular memory page is complete, and the memory page is then xe2x80x9cclosed,xe2x80x9d a precharge operation is performed to prepare the memory device for a subsequent memory access. The precharge operation requires a certain amount of time for its completion, and therefore limits the speed with which a sequence of memory operations can be performed. By organizing the memory array 202 to have multiple banks 204A and 204B with associated multiple access circuits 210A and 210B, the precharge time can, in some instances, be xe2x80x9chidden.xe2x80x9d For example, if a first memory access is to bank 204A, and a subsequent memory access is to bank 204B, precharge operations associated with bank 204A can occur while initiating memory access operations to bank 204B. However, successive memory access operations to a single bank still result in precharge time intervals during which memory access operations cannot be performed.
Some attempts have been made to minimize those data transfer interruptions caused by precharge time intervals. By leaving a page xe2x80x9copenxe2x80x9d after completing a memory access operation to that page, the precharge time penalty is avoided when a subsequent bank access is to that very same page (a xe2x80x9cpage hitxe2x80x9d). However, when a subsequent bank access is to a different page (a xe2x80x9cpage missxe2x80x9d), the open page must then be closed and the precharge operation performed before memory access operations can proceed. Therefore, while there exist benefits to leaving a page open in the event there are frequent page hits, there exist significant time penalties associated with a large number of page misses.
In accordance with the present invention, an apparatus is provided for controlling data transfer operations between a memory and a device operable to write data to and read data from the memory. The memory is organized as a plurality of pages, and a memory controller couples the device and the memory. The memory controller includes a register for storing a page address corresponding to an open page. The memory controller receives a data transfer request and an address corresponding with the requested page to or from which the data transfer is to be performed. The memory controller includes an address comparator that compares the requested page address with the stored page address to determine whether the requested page is already open. If the requested page is open, a control state machine included within the memory controller then initiates data transfer operations between the device and the requested memory page. If the requested memory page is closed, the control state machine first opens the requested memory page and subsequently initiates the data transfer operations therewith. The control state machine also determines whether the requested data transfer is a read request or a write request. If a read request, the requested memory page is left open after completion of data transfer operations. If a write request, the requested memory page is closed following completion of the data transfer operations.